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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\impl\gwsynthesis\fpga_project.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\fpga_project.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>D:\gowin_crush\gowin_proj_audio_PT8211\fpga_project\src\fpga_project.sdc</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.03 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Apr 19 12:55:28 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>1855</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>1837</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">NO.</th>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>1</td>
<td>fpga_clk_in</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>clk50mhz </td>
</tr>
<tr>
<td>2</td>
<td>usb_clk</td>
<td>Base</td>
<td>16.667</td>
<td>59.999
<td>0.000</td>
<td>8.334</td>
<td></td>
<td></td>
<td>clk60mhz </td>
</tr>
<tr>
<td>3</td>
<td>audio_clk</td>
<td>Base</td>
<td>325.521</td>
<td>3.072
<td>0.000</td>
<td>162.761</td>
<td></td>
<td></td>
<td>audio_clk </td>
</tr>
<tr>
<td>4</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>16.667</td>
<td>60.000
<td>0.000</td>
<td>8.333</td>
<td>clk50mhz_ibuf/I</td>
<td>fpga_clk_in</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>5</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>33.333</td>
<td>30.000
<td>0.000</td>
<td>16.667</td>
<td>clk50mhz_ibuf/I</td>
<td>fpga_clk_in</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>6</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>50.000</td>
<td>20.000
<td>0.000</td>
<td>25.000</td>
<td>clk50mhz_ibuf/I</td>
<td>fpga_clk_in</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>7</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>13.889</td>
<td>71.999
<td>0.000</td>
<td>6.945</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
<td>usb_clk</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>8</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>13.889</td>
<td>71.999
<td>0.000</td>
<td>6.945</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
<td>usb_clk</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>9</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>27.778</td>
<td>35.999
<td>0.000</td>
<td>13.889</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
<td>usb_clk</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>10</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>41.667</td>
<td>24.000
<td>0.000</td>
<td>20.834</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
<td>usb_clk</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>11</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>6.511</td>
<td>153.597
<td>0.000</td>
<td>3.255</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>12</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>6.511</td>
<td>153.597
<td>0.000</td>
<td>3.255</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>13</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>19.532</td>
<td>51.199
<td>0.000</td>
<td>9.766</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT</td>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD3 </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>usb_clk</td>
<td>59.999(MHz)</td>
<td>144.561(MHz)</td>
<td>8</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>audio_clk</td>
<td>3.072(MHz)</td>
<td>108.537(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of fpga_clk_in!</h4>
<h4>No timing paths to get frequency of u_clock_tree/u_usb_pll/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/your_instance_name/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/aud_pll/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/aud_pll/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of u_clock_tree/aud_pll/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>fpga_clk_in</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>fpga_clk_in</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>usb_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>usb_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>audio_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>audio_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>u_clock_tree/aud_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>9.750</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
<td>u_audio_fifo/ram_block_ram_block_0_0_s/CEA</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.830</td>
</tr>
<tr>
<td>2</td>
<td>9.899</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_7_s0/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.733</td>
</tr>
<tr>
<td>3</td>
<td>9.917</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_3_s0/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.715</td>
</tr>
<tr>
<td>4</td>
<td>9.977</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_21_s1/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.655</td>
</tr>
<tr>
<td>5</td>
<td>9.978</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_0_s0/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.654</td>
</tr>
<tr>
<td>6</td>
<td>10.026</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_5_s0/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.606</td>
</tr>
<tr>
<td>7</td>
<td>10.063</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_setup_cmd_26_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_2_s0/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.569</td>
</tr>
<tr>
<td>8</td>
<td>10.287</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_6_s0/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.345</td>
</tr>
<tr>
<td>9</td>
<td>10.302</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_setup_cmd_26_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_4_s0/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.330</td>
</tr>
<tr>
<td>10</td>
<td>10.396</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_1_s0/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.236</td>
</tr>
<tr>
<td>11</td>
<td>10.436</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_18_s1/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.196</td>
</tr>
<tr>
<td>12</td>
<td>10.498</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
<td>u_audio_fifo/wr_counter_0_s3/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.134</td>
</tr>
<tr>
<td>13</td>
<td>10.514</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
<td>u_audio_fifo/wr_counter_1_s0/CE</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.118</td>
</tr>
<tr>
<td>14</td>
<td>10.514</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
<td>u_audio_fifo/wr_counter_2_s0/CE</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.118</td>
</tr>
<tr>
<td>15</td>
<td>10.514</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
<td>u_audio_fifo/wr_counter_3_s0/CE</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.118</td>
</tr>
<tr>
<td>16</td>
<td>10.520</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_19_s1/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.112</td>
</tr>
<tr>
<td>17</td>
<td>10.546</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
<td>u_audio_fifo/wr_counter_5_s0/CE</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.086</td>
</tr>
<tr>
<td>18</td>
<td>10.546</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
<td>u_audio_fifo/wr_counter_4_s0/CE</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>6.086</td>
</tr>
<tr>
<td>19</td>
<td>10.633</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_23_s1/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>5.999</td>
</tr>
<tr>
<td>20</td>
<td>10.669</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_25_s1/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>5.963</td>
</tr>
<tr>
<td>21</td>
<td>10.721</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_24_s1/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>5.911</td>
</tr>
<tr>
<td>22</td>
<td>10.760</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_26_s1/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>5.872</td>
</tr>
<tr>
<td>23</td>
<td>10.776</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/dnl_1_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s1/CE</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>5.856</td>
</tr>
<tr>
<td>24</td>
<td>10.791</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_20_s1/D</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>5.841</td>
</tr>
<tr>
<td>25</td>
<td>10.831</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/dnl_1_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_2_s1/CE</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>5.801</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.074</td>
<td>u_usb_audio/o_pcm_7_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[7]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.323</td>
</tr>
<tr>
<td>2</td>
<td>0.077</td>
<td>u_usb_audio/o_pcm_28_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[28]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.326</td>
</tr>
<tr>
<td>3</td>
<td>0.077</td>
<td>u_usb_audio/o_pcm_23_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[23]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.326</td>
</tr>
<tr>
<td>4</td>
<td>0.077</td>
<td>u_usb_audio/o_pcm_16_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[16]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.326</td>
</tr>
<tr>
<td>5</td>
<td>0.077</td>
<td>u_usb_audio/o_pcm_8_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[8]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.326</td>
</tr>
<tr>
<td>6</td>
<td>0.198</td>
<td>u_usb_audio/audio_lo_1_s0/Q</td>
<td>u_audio_fifo/ram_block_ram_block_0_0_s/DI[1]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.447</td>
</tr>
<tr>
<td>7</td>
<td>0.202</td>
<td>u_usb_audio/o_pcm_5_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[5]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.451</td>
</tr>
<tr>
<td>8</td>
<td>0.203</td>
<td>u_usb_audio/o_pcm_17_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[17]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.452</td>
</tr>
<tr>
<td>9</td>
<td>0.213</td>
<td>u_usb_audio/o_pcm_2_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[2]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>10</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_31_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[31]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>11</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_30_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[30]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>12</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_29_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[29]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>13</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_22_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[22]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>14</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_21_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[21]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>15</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_19_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[19]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>16</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_18_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[18]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>17</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_15_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[15]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>18</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_14_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[14]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>19</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_13_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[13]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>20</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_12_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[12]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>21</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_11_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[11]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>22</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_10_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[10]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>23</td>
<td>0.215</td>
<td>u_usb_audio/o_pcm_9_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[9]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.464</td>
</tr>
<tr>
<td>24</td>
<td>0.216</td>
<td>u_usb_audio/o_pcm_20_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[20]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.465</td>
</tr>
<tr>
<td>25</td>
<td>0.324</td>
<td>u_usb_audio/o_pcm_6_s0/Q</td>
<td>u_usb_audio/bufo_bufo_0_0_s/DI[6]</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.573</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>2</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>3</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>4</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>5</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>6</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>7</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>8</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>9</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>10</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>11</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>12</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>13</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>14</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>15</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>16</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>17</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>18</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>19</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>20</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>21</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>22</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>23</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>24</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
<tr>
<td>25</td>
<td>15.073</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>16.667</td>
<td>0.000</td>
<td>1.559</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>2</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>3</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>4</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>5</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>6</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>7</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>8</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>9</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>10</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>11</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>12</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>13</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>14</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>15</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>16</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>17</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>18</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>19</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>20</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>21</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>22</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>23</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>24</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
<tr>
<td>25</td>
<td>1.047</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLEAR</td>
<td>usb_clk:[R]</td>
<td>usb_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>1.058</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_audio_fifo/wr_counter_4_s0</td>
</tr>
<tr>
<td>2</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_audio_fifo/wr_counter_2_s0</td>
</tr>
<tr>
<td>3</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_audio_fifo/rd_counter_green_sync0_3_s0</td>
</tr>
<tr>
<td>4</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_audio_fifo/rd_counter_green_sync1_1_s0</td>
</tr>
<tr>
<td>5</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_usb_audio/o_pcm_31_s0</td>
</tr>
<tr>
<td>6</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_usb_audio/o_pcm_en_s0</td>
</tr>
<tr>
<td>7</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_27_s1</td>
</tr>
<tr>
<td>8</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_packet_rx/rx_shift_4_s3</td>
</tr>
<tr>
<td>9</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_packet_rx/rx_shift_5_s3</td>
</tr>
<tr>
<td>10</td>
<td>6.570</td>
<td>7.570</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>usb_clk</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_28_s1</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.750</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.102</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.851</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/ram_block_ram_block_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
</tr>
<tr>
<td>3.179</td>
<td>0.675</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[2][B]</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I3</td>
</tr>
<tr>
<td>3.734</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R17C18[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>4.400</td>
<td>0.666</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][B]</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>4.771</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>4.784</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][A]</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>5.301</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>5.723</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[0][B]</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>6.293</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>6.293</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C24[1][A]</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>6.328</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>6.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[1][B]</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>6.363</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>6.363</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][A]</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>6.398</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>6.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][B]</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>6.434</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>6.434</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C25[0][A]</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>6.904</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>7.151</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C23[3][A]</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>7.522</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>8.020</td>
<td>0.499</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C23[3][A]</td>
<td>u_audio_fifo/ram_block_s4/I2</td>
</tr>
<tr>
<td>8.590</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R14C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/ram_block_s4/F</td>
</tr>
<tr>
<td>9.102</td>
<td>0.512</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[6]</td>
<td style=" font-weight:bold;">u_audio_fifo/ram_block_ram_block_0_0_s/CEA</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[6]</td>
<td>u_audio_fifo/ram_block_ram_block_0_0_s/CLKA</td>
</tr>
<tr>
<td>18.851</td>
<td>-0.087</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[6]</td>
<td>u_audio_fifo/ram_block_ram_block_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.565, 52.190%; route: 3.034, 44.414%; tC2Q: 0.232, 3.397%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.899</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.004</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>60</td>
<td>R29C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
</tr>
<tr>
<td>3.955</td>
<td>1.451</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/I0</td>
</tr>
<tr>
<td>4.472</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>11</td>
<td>R29C31[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/F</td>
</tr>
<tr>
<td>5.227</td>
<td>0.756</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C34[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/I3</td>
</tr>
<tr>
<td>5.598</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C34[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/F</td>
</tr>
<tr>
<td>6.296</td>
<td>0.697</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s14/I1</td>
</tr>
<tr>
<td>6.749</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R30C38[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s14/F</td>
</tr>
<tr>
<td>7.316</td>
<td>0.567</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C38[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2182_s9/I3</td>
</tr>
<tr>
<td>7.769</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C38[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2182_s9/F</td>
</tr>
<tr>
<td>8.434</td>
<td>0.665</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2182_s7/I2</td>
</tr>
<tr>
<td>9.004</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2182_s7/F</td>
</tr>
<tr>
<td>9.004</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C33[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_7_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C33[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.364, 35.113%; route: 4.137, 61.441%; tC2Q: 0.232, 3.446%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.917</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.987</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>60</td>
<td>R29C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
</tr>
<tr>
<td>3.955</td>
<td>1.451</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/I0</td>
</tr>
<tr>
<td>4.472</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>11</td>
<td>R29C31[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/F</td>
</tr>
<tr>
<td>5.227</td>
<td>0.756</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C34[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/I3</td>
</tr>
<tr>
<td>5.598</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C34[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/F</td>
</tr>
<tr>
<td>6.296</td>
<td>0.697</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s14/I1</td>
</tr>
<tr>
<td>6.749</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R30C38[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s14/F</td>
</tr>
<tr>
<td>7.316</td>
<td>0.567</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C38[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2182_s9/I3</td>
</tr>
<tr>
<td>7.778</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R27C38[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2182_s9/F</td>
</tr>
<tr>
<td>7.953</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C37[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2190_s40/I3</td>
</tr>
<tr>
<td>8.415</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R27C37[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2190_s40/F</td>
</tr>
<tr>
<td>8.417</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C37[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2190_s11/I3</td>
</tr>
<tr>
<td>8.987</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R27C37[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2190_s11/F</td>
</tr>
<tr>
<td>8.987</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C37[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C37[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_3_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C37[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.835, 42.216%; route: 3.648, 54.329%; tC2Q: 0.232, 3.455%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.977</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.926</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_21_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
</tr>
<tr>
<td>3.080</td>
<td>0.576</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n137_s3/I1</td>
</tr>
<tr>
<td>3.533</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C29[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n137_s3/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.510</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C27[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n133_s3/I3</td>
</tr>
<tr>
<td>4.598</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C27[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n133_s3/F</td>
</tr>
<tr>
<td>5.348</td>
<td>0.750</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n126_s3/I3</td>
</tr>
<tr>
<td>5.865</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C30[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n126_s3/F</td>
</tr>
<tr>
<td>6.535</td>
<td>0.670</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C28[1][A]</td>
<td>u_usb_audio/usbfs_core_i/n120_s4/I3</td>
</tr>
<tr>
<td>7.090</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R21C28[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n120_s4/F</td>
</tr>
<tr>
<td>7.496</td>
<td>0.406</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C28[1][A]</td>
<td>u_usb_audio/usbfs_core_i/n120_s3/I3</td>
</tr>
<tr>
<td>8.051</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C28[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n120_s3/F</td>
</tr>
<tr>
<td>8.464</td>
<td>0.413</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/n120_s1/I1</td>
</tr>
<tr>
<td>8.926</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R23C30[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n120_s1/F</td>
</tr>
<tr>
<td>8.926</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C30[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_21_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_21_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R23C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_21_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.097, 46.538%; route: 3.326, 49.976%; tC2Q: 0.232, 3.486%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>9.978</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.926</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>60</td>
<td>R29C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
</tr>
<tr>
<td>3.955</td>
<td>1.451</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/I0</td>
</tr>
<tr>
<td>4.472</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>11</td>
<td>R29C31[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/F</td>
</tr>
<tr>
<td>5.188</td>
<td>0.716</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C35[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s62/I1</td>
</tr>
<tr>
<td>5.559</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C35[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s62/F</td>
</tr>
<tr>
<td>5.713</td>
<td>0.154</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C35[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s43/I2</td>
</tr>
<tr>
<td>6.268</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R26C35[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s43/F</td>
</tr>
<tr>
<td>6.924</td>
<td>0.656</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C36[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s22/I3</td>
</tr>
<tr>
<td>7.479</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R29C36[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s22/F</td>
</tr>
<tr>
<td>7.892</td>
<td>0.413</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C35[3][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s14/I2</td>
</tr>
<tr>
<td>8.462</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R31C35[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s14/F</td>
</tr>
<tr>
<td>8.464</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C35[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s12/I2</td>
</tr>
<tr>
<td>8.926</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R31C35[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2196_s12/F</td>
</tr>
<tr>
<td>8.926</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C35[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C35[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_0_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C35[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.030, 45.535%; route: 3.392, 50.978%; tC2Q: 0.232, 3.487%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.026</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.877</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>60</td>
<td>R29C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
</tr>
<tr>
<td>3.955</td>
<td>1.451</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/I0</td>
</tr>
<tr>
<td>4.472</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>11</td>
<td>R29C31[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/F</td>
</tr>
<tr>
<td>5.227</td>
<td>0.756</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C34[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/I3</td>
</tr>
<tr>
<td>5.598</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C34[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/F</td>
</tr>
<tr>
<td>6.296</td>
<td>0.697</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s14/I1</td>
</tr>
<tr>
<td>6.749</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R30C38[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s14/F</td>
</tr>
<tr>
<td>7.409</td>
<td>0.660</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C39[3][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2186_s23/I2</td>
</tr>
<tr>
<td>7.780</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R27C39[3][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2186_s23/F</td>
</tr>
<tr>
<td>7.785</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C39[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2186_s13/I3</td>
</tr>
<tr>
<td>8.334</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C39[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2186_s13/F</td>
</tr>
<tr>
<td>8.506</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2186_s10/I3</td>
</tr>
<tr>
<td>8.877</td>
<td>0.371</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R26C39[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2186_s10/F</td>
</tr>
<tr>
<td>8.877</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R26C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_5_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R26C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.632, 39.844%; route: 3.742, 56.643%; tC2Q: 0.232, 3.512%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.063</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.840</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_setup_cmd_26_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C29[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_setup_cmd_26_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R30C29[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_setup_cmd_26_s0/Q</td>
</tr>
<tr>
<td>3.404</td>
<td>0.901</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C32[3][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2190_s32/I0</td>
</tr>
<tr>
<td>3.775</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C32[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2190_s32/F</td>
</tr>
<tr>
<td>4.343</td>
<td>0.567</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C33[3][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s16/I2</td>
</tr>
<tr>
<td>4.714</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R27C33[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s16/F</td>
</tr>
<tr>
<td>5.645</td>
<td>0.931</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C36[3][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2184_s27/I2</td>
</tr>
<tr>
<td>6.098</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R30C36[3][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2184_s27/F</td>
</tr>
<tr>
<td>6.989</td>
<td>0.891</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C37[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s18/I3</td>
</tr>
<tr>
<td>7.506</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R30C37[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s18/F</td>
</tr>
<tr>
<td>7.919</td>
<td>0.413</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C38[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s13/I0</td>
</tr>
<tr>
<td>8.468</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R31C38[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s13/F</td>
</tr>
<tr>
<td>8.469</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s10/I2</td>
</tr>
<tr>
<td>8.840</td>
<td>0.371</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R31C38[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s10/F</td>
</tr>
<tr>
<td>8.840</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C38[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_2_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.632, 40.066%; route: 3.705, 56.402%; tC2Q: 0.232, 3.532%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.287</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.617</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>60</td>
<td>R29C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
</tr>
<tr>
<td>3.955</td>
<td>1.451</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/I0</td>
</tr>
<tr>
<td>4.472</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>11</td>
<td>R29C31[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/F</td>
</tr>
<tr>
<td>5.227</td>
<td>0.756</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C34[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/I3</td>
</tr>
<tr>
<td>5.598</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C34[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/F</td>
</tr>
<tr>
<td>6.296</td>
<td>0.697</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s14/I1</td>
</tr>
<tr>
<td>6.749</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R30C38[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s14/F</td>
</tr>
<tr>
<td>7.316</td>
<td>0.567</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C38[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2182_s9/I3</td>
</tr>
<tr>
<td>7.769</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C38[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2182_s9/F</td>
</tr>
<tr>
<td>7.782</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C38[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2184_s13/I2</td>
</tr>
<tr>
<td>8.244</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R27C38[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2184_s13/F</td>
</tr>
<tr>
<td>8.246</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2184_s10/I2</td>
</tr>
<tr>
<td>8.617</td>
<td>0.371</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R27C38[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2184_s10/F</td>
</tr>
<tr>
<td>8.617</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C38[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_6_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.627, 41.400%; route: 3.486, 54.944%; tC2Q: 0.232, 3.656%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.302</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.601</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_setup_cmd_26_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C29[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_setup_cmd_26_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R30C29[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_setup_cmd_26_s0/Q</td>
</tr>
<tr>
<td>3.404</td>
<td>0.901</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C32[3][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2190_s32/I0</td>
</tr>
<tr>
<td>3.775</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C32[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2190_s32/F</td>
</tr>
<tr>
<td>4.343</td>
<td>0.567</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C33[3][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s16/I2</td>
</tr>
<tr>
<td>4.714</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R27C33[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s16/F</td>
</tr>
<tr>
<td>5.645</td>
<td>0.931</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C36[3][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2184_s27/I2</td>
</tr>
<tr>
<td>6.098</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R30C36[3][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2184_s27/F</td>
</tr>
<tr>
<td>6.867</td>
<td>0.770</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C40[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s18/I3</td>
</tr>
<tr>
<td>7.416</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R30C40[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s18/F</td>
</tr>
<tr>
<td>7.589</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C40[3][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s13/I2</td>
</tr>
<tr>
<td>8.138</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R31C40[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s13/F</td>
</tr>
<tr>
<td>8.139</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C40[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s10/I3</td>
</tr>
<tr>
<td>8.601</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R31C40[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s10/F</td>
</tr>
<tr>
<td>8.601</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C40[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C40[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_4_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C40[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.755, 43.525%; route: 3.343, 52.810%; tC2Q: 0.232, 3.665%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.396</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.507</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>60</td>
<td>R29C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/Q</td>
</tr>
<tr>
<td>3.955</td>
<td>1.451</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C31[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/I0</td>
</tr>
<tr>
<td>4.472</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>11</td>
<td>R29C31[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2192_s25/F</td>
</tr>
<tr>
<td>5.227</td>
<td>0.756</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C34[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/I3</td>
</tr>
<tr>
<td>5.598</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R27C34[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2188_s19/F</td>
</tr>
<tr>
<td>6.268</td>
<td>0.669</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C33[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2194_s36/I3</td>
</tr>
<tr>
<td>6.730</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R30C33[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2194_s36/F</td>
</tr>
<tr>
<td>6.902</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C33[3][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2194_s20/I3</td>
</tr>
<tr>
<td>7.472</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R31C33[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2194_s20/F</td>
</tr>
<tr>
<td>7.474</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C33[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2194_s13/I3</td>
</tr>
<tr>
<td>7.936</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R31C33[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2194_s13/F</td>
</tr>
<tr>
<td>7.937</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C33[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2194_s11/I2</td>
</tr>
<tr>
<td>8.507</td>
<td>0.570</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R31C33[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/n2194_s11/F</td>
</tr>
<tr>
<td>8.507</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C33[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C33[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_1_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C33[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_data_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.952, 47.342%; route: 3.052, 48.938%; tC2Q: 0.232, 3.721%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.436</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.467</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_18_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
</tr>
<tr>
<td>3.080</td>
<td>0.576</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n137_s3/I1</td>
</tr>
<tr>
<td>3.533</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C29[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n137_s3/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.510</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C27[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n133_s3/I3</td>
</tr>
<tr>
<td>4.598</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C27[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n133_s3/F</td>
</tr>
<tr>
<td>5.348</td>
<td>0.750</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n126_s3/I3</td>
</tr>
<tr>
<td>5.865</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C30[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n126_s3/F</td>
</tr>
<tr>
<td>6.535</td>
<td>0.670</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C28[1][A]</td>
<td>u_usb_audio/usbfs_core_i/n120_s4/I3</td>
</tr>
<tr>
<td>7.105</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R21C28[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n120_s4/F</td>
</tr>
<tr>
<td>7.284</td>
<td>0.178</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C29[0][B]</td>
<td>u_usb_audio/usbfs_core_i/n123_s2/I0</td>
</tr>
<tr>
<td>7.833</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C29[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n123_s2/F</td>
</tr>
<tr>
<td>8.005</td>
<td>0.172</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C30[1][B]</td>
<td>u_usb_audio/usbfs_core_i/n123_s1/I3</td>
</tr>
<tr>
<td>8.467</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C30[1][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n123_s1/F</td>
</tr>
<tr>
<td>8.467</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C30[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_18_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C30[1][B]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_18_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C30[1][B]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_18_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.106, 50.131%; route: 2.858, 46.124%; tC2Q: 0.232, 3.745%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.498</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.406</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
</tr>
<tr>
<td>3.179</td>
<td>0.675</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[2][B]</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I3</td>
</tr>
<tr>
<td>3.734</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R17C18[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>4.400</td>
<td>0.666</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][B]</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>4.771</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>4.784</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][A]</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>5.301</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>5.723</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[0][B]</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>6.293</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>6.293</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C24[1][A]</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>6.328</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>6.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[1][B]</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>6.363</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>6.363</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][A]</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>6.398</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>6.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][B]</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>6.434</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>6.434</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C25[0][A]</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>6.904</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>7.151</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C23[3][A]</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>7.522</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.944</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C24[0][A]</td>
<td>u_audio_fifo/n13_s3/I2</td>
</tr>
<tr>
<td>8.406</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R17C24[0][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n13_s3/F</td>
</tr>
<tr>
<td>8.406</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C24[0][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/wr_counter_0_s3/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C24[0][A]</td>
<td>u_audio_fifo/wr_counter_0_s3/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R17C24[0][A]</td>
<td>u_audio_fifo/wr_counter_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.457, 56.352%; route: 2.445, 39.866%; tC2Q: 0.232, 3.782%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.514</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.389</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
</tr>
<tr>
<td>3.179</td>
<td>0.675</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[2][B]</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I3</td>
</tr>
<tr>
<td>3.734</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R17C18[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>4.400</td>
<td>0.666</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][B]</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>4.771</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>4.784</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][A]</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>5.301</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>5.723</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[0][B]</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>6.293</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>6.293</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C24[1][A]</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>6.328</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>6.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[1][B]</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>6.363</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>6.363</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][A]</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>6.398</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>6.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][B]</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>6.434</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>6.434</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C25[0][A]</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>6.904</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>7.151</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C23[3][A]</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>7.522</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.701</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[3][A]</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>8.028</td>
<td>0.327</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R18C24[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.389</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C21[1][B]</td>
<td style=" font-weight:bold;">u_audio_fifo/wr_counter_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C21[1][B]</td>
<td>u_audio_fifo/wr_counter_1_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C21[1][B]</td>
<td>u_audio_fifo/wr_counter_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.322, 54.298%; route: 2.564, 41.909%; tC2Q: 0.232, 3.792%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.514</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.389</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
</tr>
<tr>
<td>3.179</td>
<td>0.675</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[2][B]</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I3</td>
</tr>
<tr>
<td>3.734</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R17C18[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>4.400</td>
<td>0.666</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][B]</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>4.771</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>4.784</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][A]</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>5.301</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>5.723</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[0][B]</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>6.293</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>6.293</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C24[1][A]</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>6.328</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>6.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[1][B]</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>6.363</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>6.363</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][A]</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>6.398</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>6.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][B]</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>6.434</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>6.434</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C25[0][A]</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>6.904</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>7.151</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C23[3][A]</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>7.522</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.701</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[3][A]</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>8.028</td>
<td>0.327</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R18C24[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.389</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C21[2][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/wr_counter_2_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C21[2][A]</td>
<td>u_audio_fifo/wr_counter_2_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C21[2][A]</td>
<td>u_audio_fifo/wr_counter_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.322, 54.298%; route: 2.564, 41.909%; tC2Q: 0.232, 3.792%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.514</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.389</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
</tr>
<tr>
<td>3.179</td>
<td>0.675</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[2][B]</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I3</td>
</tr>
<tr>
<td>3.734</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R17C18[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>4.400</td>
<td>0.666</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][B]</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>4.771</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>4.784</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][A]</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>5.301</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>5.723</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[0][B]</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>6.293</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>6.293</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C24[1][A]</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>6.328</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>6.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[1][B]</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>6.363</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>6.363</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][A]</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>6.398</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>6.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][B]</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>6.434</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>6.434</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C25[0][A]</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>6.904</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>7.151</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C23[3][A]</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>7.522</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.701</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[3][A]</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>8.028</td>
<td>0.327</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R18C24[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.389</td>
<td>0.361</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C21[2][B]</td>
<td style=" font-weight:bold;">u_audio_fifo/wr_counter_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C21[2][B]</td>
<td>u_audio_fifo/wr_counter_3_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C21[2][B]</td>
<td>u_audio_fifo/wr_counter_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.322, 54.298%; route: 2.564, 41.909%; tC2Q: 0.232, 3.792%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.520</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.383</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_19_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
</tr>
<tr>
<td>3.080</td>
<td>0.576</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n137_s3/I1</td>
</tr>
<tr>
<td>3.533</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C29[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n137_s3/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.510</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C27[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n133_s3/I3</td>
</tr>
<tr>
<td>4.598</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C27[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n133_s3/F</td>
</tr>
<tr>
<td>5.348</td>
<td>0.750</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n126_s3/I3</td>
</tr>
<tr>
<td>5.865</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C30[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n126_s3/F</td>
</tr>
<tr>
<td>6.535</td>
<td>0.670</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C28[1][A]</td>
<td>u_usb_audio/usbfs_core_i/n120_s4/I3</td>
</tr>
<tr>
<td>7.105</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R21C28[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n120_s4/F</td>
</tr>
<tr>
<td>7.284</td>
<td>0.178</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C29[3][B]</td>
<td>u_usb_audio/usbfs_core_i/n122_s2/I1</td>
</tr>
<tr>
<td>7.833</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C29[3][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n122_s2/F</td>
</tr>
<tr>
<td>7.834</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/n122_s1/I1</td>
</tr>
<tr>
<td>8.383</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R21C29[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n122_s1/F</td>
</tr>
<tr>
<td>8.383</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_19_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_19_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_19_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.193, 52.245%; route: 2.687, 43.959%; tC2Q: 0.232, 3.796%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.357</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
</tr>
<tr>
<td>3.179</td>
<td>0.675</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[2][B]</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I3</td>
</tr>
<tr>
<td>3.734</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R17C18[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>4.400</td>
<td>0.666</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][B]</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>4.771</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>4.784</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][A]</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>5.301</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>5.723</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[0][B]</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>6.293</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>6.293</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C24[1][A]</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>6.328</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>6.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[1][B]</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>6.363</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>6.363</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][A]</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>6.398</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>6.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][B]</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>6.434</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>6.434</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C25[0][A]</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>6.904</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>7.151</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C23[3][A]</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>7.522</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.701</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[3][A]</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>8.028</td>
<td>0.327</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R18C24[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.357</td>
<td>0.329</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][B]</td>
<td style=" font-weight:bold;">u_audio_fifo/wr_counter_5_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][B]</td>
<td>u_audio_fifo/wr_counter_5_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C22[0][B]</td>
<td>u_audio_fifo/wr_counter_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.322, 54.583%; route: 2.532, 41.604%; tC2Q: 0.232, 3.812%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.546</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.357</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/wr_counter_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C21[1][A]</td>
<td>u_audio_fifo/rd_counter_green_sync1_4_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R17C21[1][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/rd_counter_green_sync1_4_s0/Q</td>
</tr>
<tr>
<td>3.179</td>
<td>0.675</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C18[2][B]</td>
<td>u_audio_fifo/rd_counter_bin_2_s1/I3</td>
</tr>
<tr>
<td>3.734</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R17C18[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_2_s1/F</td>
</tr>
<tr>
<td>4.400</td>
<td>0.666</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][B]</td>
<td>u_audio_fifo/rd_counter_bin_1_s0/I1</td>
</tr>
<tr>
<td>4.771</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_1_s0/F</td>
</tr>
<tr>
<td>4.784</td>
<td>0.013</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R17C23[3][A]</td>
<td>u_audio_fifo/rd_counter_bin_0_s0/I1</td>
</tr>
<tr>
<td>5.301</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R17C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/rd_counter_bin_0_s0/F</td>
</tr>
<tr>
<td>5.723</td>
<td>0.422</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[0][B]</td>
<td>u_audio_fifo/n322_s/I0</td>
</tr>
<tr>
<td>6.293</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C24[0][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n322_s/COUT</td>
</tr>
<tr>
<td>6.293</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>R18C24[1][A]</td>
<td>u_audio_fifo/n321_s/CIN</td>
</tr>
<tr>
<td>6.328</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C24[1][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n321_s/COUT</td>
</tr>
<tr>
<td>6.328</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[1][B]</td>
<td>u_audio_fifo/n320_s/CIN</td>
</tr>
<tr>
<td>6.363</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[1][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n320_s/COUT</td>
</tr>
<tr>
<td>6.363</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][A]</td>
<td>u_audio_fifo/n319_s/CIN</td>
</tr>
<tr>
<td>6.398</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n319_s/COUT</td>
</tr>
<tr>
<td>6.398</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C24[2][B]</td>
<td>u_audio_fifo/n318_s/CIN</td>
</tr>
<tr>
<td>6.434</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C24[2][B]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n318_s/COUT</td>
</tr>
<tr>
<td>6.434</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C25[0][A]</td>
<td>u_audio_fifo/n317_s/CIN</td>
</tr>
<tr>
<td>6.904</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C25[0][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n317_s/SUM</td>
</tr>
<tr>
<td>7.151</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C23[3][A]</td>
<td>u_audio_fifo/n6_s1/I0</td>
</tr>
<tr>
<td>7.522</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R18C23[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s1/F</td>
</tr>
<tr>
<td>7.701</td>
<td>0.179</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C24[3][A]</td>
<td>u_audio_fifo/n6_s4/I1</td>
</tr>
<tr>
<td>8.028</td>
<td>0.327</td>
<td>tINS</td>
<td>FR</td>
<td>5</td>
<td>R18C24[3][A]</td>
<td style=" background: #97FFFF;">u_audio_fifo/n6_s4/F</td>
</tr>
<tr>
<td>8.357</td>
<td>0.329</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][A]</td>
<td style=" font-weight:bold;">u_audio_fifo/wr_counter_4_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C22[0][A]</td>
<td>u_audio_fifo/wr_counter_4_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R18C22[0][A]</td>
<td>u_audio_fifo/wr_counter_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.322, 54.583%; route: 2.532, 41.604%; tC2Q: 0.232, 3.812%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.633</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.270</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_23_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
</tr>
<tr>
<td>3.080</td>
<td>0.576</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n137_s3/I1</td>
</tr>
<tr>
<td>3.533</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C29[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n137_s3/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.510</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C27[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n133_s3/I3</td>
</tr>
<tr>
<td>4.598</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C27[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n133_s3/F</td>
</tr>
<tr>
<td>5.348</td>
<td>0.750</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n126_s3/I3</td>
</tr>
<tr>
<td>5.865</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C30[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n126_s3/F</td>
</tr>
<tr>
<td>6.535</td>
<td>0.670</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/n119_s3/I1</td>
</tr>
<tr>
<td>7.084</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>2</td>
<td>R23C30[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n119_s3/F</td>
</tr>
<tr>
<td>7.258</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/n118_s2/I0</td>
</tr>
<tr>
<td>7.807</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R24C30[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n118_s2/F</td>
</tr>
<tr>
<td>7.808</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/n118_s1/I2</td>
</tr>
<tr>
<td>8.270</td>
<td>0.462</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R24C30[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n118_s1/F</td>
</tr>
<tr>
<td>8.270</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C30[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_23_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R24C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_23_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R24C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_23_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.085, 51.425%; route: 2.682, 44.708%; tC2Q: 0.232, 3.867%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.669</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.234</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_25_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
</tr>
<tr>
<td>3.080</td>
<td>0.576</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n137_s3/I1</td>
</tr>
<tr>
<td>3.533</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C29[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n137_s3/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.510</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C27[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n133_s3/I3</td>
</tr>
<tr>
<td>4.598</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C27[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n133_s3/F</td>
</tr>
<tr>
<td>5.348</td>
<td>0.750</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n126_s3/I3</td>
</tr>
<tr>
<td>5.865</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C30[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n126_s3/F</td>
</tr>
<tr>
<td>6.535</td>
<td>0.670</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C30[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n115_s5/I3</td>
</tr>
<tr>
<td>7.052</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R23C30[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n115_s5/F</td>
</tr>
<tr>
<td>7.309</td>
<td>0.257</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C30[3][B]</td>
<td>u_usb_audio/usbfs_core_i/n116_s3/I1</td>
</tr>
<tr>
<td>7.680</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R21C30[3][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n116_s3/F</td>
</tr>
<tr>
<td>7.685</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/n116_s1/I2</td>
</tr>
<tr>
<td>8.234</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C30[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n116_s1/F</td>
</tr>
<tr>
<td>8.234</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C30[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_25_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_25_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_25_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.962, 49.677%; route: 2.769, 46.432%; tC2Q: 0.232, 3.891%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.721</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.182</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_24_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
</tr>
<tr>
<td>3.080</td>
<td>0.576</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n137_s3/I1</td>
</tr>
<tr>
<td>3.533</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C29[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n137_s3/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.510</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C27[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n133_s3/I3</td>
</tr>
<tr>
<td>4.598</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C27[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n133_s3/F</td>
</tr>
<tr>
<td>5.348</td>
<td>0.750</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n126_s3/I3</td>
</tr>
<tr>
<td>5.865</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C30[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n126_s3/F</td>
</tr>
<tr>
<td>6.535</td>
<td>0.670</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C30[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n115_s5/I3</td>
</tr>
<tr>
<td>7.084</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>R23C30[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n115_s5/F</td>
</tr>
<tr>
<td>7.258</td>
<td>0.174</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C30[3][B]</td>
<td>u_usb_audio/usbfs_core_i/n117_s2/I1</td>
</tr>
<tr>
<td>7.629</td>
<td>0.371</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R22C30[3][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n117_s2/F</td>
</tr>
<tr>
<td>7.633</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/n117_s1/I3</td>
</tr>
<tr>
<td>8.182</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R22C30[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n117_s1/F</td>
</tr>
<tr>
<td>8.182</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C30[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_24_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_24_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_24_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.994, 50.650%; route: 2.685, 45.425%; tC2Q: 0.232, 3.925%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.760</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.144</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_26_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
</tr>
<tr>
<td>3.080</td>
<td>0.576</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n137_s3/I1</td>
</tr>
<tr>
<td>3.533</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C29[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n137_s3/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.510</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C27[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n133_s3/I3</td>
</tr>
<tr>
<td>4.598</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C27[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n133_s3/F</td>
</tr>
<tr>
<td>5.348</td>
<td>0.750</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n126_s3/I3</td>
</tr>
<tr>
<td>5.865</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C30[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n126_s3/F</td>
</tr>
<tr>
<td>6.535</td>
<td>0.670</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R23C30[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n115_s5/I3</td>
</tr>
<tr>
<td>7.052</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R23C30[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n115_s5/F</td>
</tr>
<tr>
<td>7.309</td>
<td>0.257</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C30[1][A]</td>
<td>u_usb_audio/usbfs_core_i/n115_s4/I2</td>
</tr>
<tr>
<td>7.771</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C30[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n115_s4/F</td>
</tr>
<tr>
<td>7.773</td>
<td>0.001</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/n115_s1/I2</td>
</tr>
<tr>
<td>8.144</td>
<td>0.371</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C30[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n115_s1/F</td>
</tr>
<tr>
<td>8.144</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C30[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_26_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_26_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_26_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.875, 48.957%; route: 2.765, 47.092%; tC2Q: 0.232, 3.951%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.776</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.127</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/dnl_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C37[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/dnl_1_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R20C37[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/dnl_1_s0/Q</td>
</tr>
<tr>
<td>3.407</td>
<td>0.903</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C37[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/n446_s4/I1</td>
</tr>
<tr>
<td>3.778</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C37[1][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/n446_s4/F</td>
</tr>
<tr>
<td>4.210</td>
<td>0.432</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C38[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/n442_s50/I2</td>
</tr>
<tr>
<td>4.581</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R21C38[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/n442_s50/F</td>
</tr>
<tr>
<td>4.765</td>
<td>0.184</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C38[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/n451_s9/I1</td>
</tr>
<tr>
<td>5.314</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R22C38[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/n451_s9/F</td>
</tr>
<tr>
<td>5.319</td>
<td>0.005</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C38[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_0_s9/I3</td>
</tr>
<tr>
<td>5.868</td>
<td>0.549</td>
<td>tINS</td>
<td>RR</td>
<td>3</td>
<td>R22C38[1][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_0_s9/F</td>
</tr>
<tr>
<td>6.045</td>
<td>0.177</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C39[3][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s8/I1</td>
</tr>
<tr>
<td>6.416</td>
<td>0.371</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R22C39[3][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s8/F</td>
</tr>
<tr>
<td>7.076</td>
<td>0.660</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C40[3][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s6/I1</td>
</tr>
<tr>
<td>7.403</td>
<td>0.327</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R22C40[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s6/F</td>
</tr>
<tr>
<td>8.127</td>
<td>0.724</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C40[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C40[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C40[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.538, 43.343%; route: 3.086, 52.694%; tC2Q: 0.232, 3.962%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.791</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.113</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_20_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R20C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_1_s1/Q</td>
</tr>
<tr>
<td>3.080</td>
<td>0.576</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C29[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n137_s3/I1</td>
</tr>
<tr>
<td>3.533</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C29[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n137_s3/F</td>
</tr>
<tr>
<td>4.043</td>
<td>0.510</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C27[3][A]</td>
<td>u_usb_audio/usbfs_core_i/n133_s3/I3</td>
</tr>
<tr>
<td>4.598</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C27[3][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n133_s3/F</td>
</tr>
<tr>
<td>5.348</td>
<td>0.750</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/n126_s3/I3</td>
</tr>
<tr>
<td>5.865</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>R18C30[2][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n126_s3/F</td>
</tr>
<tr>
<td>6.535</td>
<td>0.670</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C28[1][A]</td>
<td>u_usb_audio/usbfs_core_i/n120_s4/I3</td>
</tr>
<tr>
<td>7.105</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>4</td>
<td>R21C28[1][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n120_s4/F</td>
</tr>
<tr>
<td>7.109</td>
<td>0.004</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C28[0][B]</td>
<td>u_usb_audio/usbfs_core_i/n121_s2/I2</td>
</tr>
<tr>
<td>7.480</td>
<td>0.371</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R21C28[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n121_s2/F</td>
</tr>
<tr>
<td>7.651</td>
<td>0.170</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R21C29[2][A]</td>
<td>u_usb_audio/usbfs_core_i/n121_s1/I1</td>
</tr>
<tr>
<td>8.113</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R21C29[2][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/n121_s1/F</td>
</tr>
<tr>
<td>8.113</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C29[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_cnt_20_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R21C29[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_20_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R21C29[2][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_20_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>7</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.928, 50.125%; route: 2.681, 45.903%; tC2Q: 0.232, 3.972%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>10.831</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.073</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/dnl_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C37[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/dnl_1_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R20C37[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/dnl_1_s0/Q</td>
</tr>
<tr>
<td>3.407</td>
<td>0.903</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R20C37[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/n446_s4/I1</td>
</tr>
<tr>
<td>3.778</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>6</td>
<td>R20C37[1][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/n446_s4/F</td>
</tr>
<tr>
<td>4.204</td>
<td>0.427</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C38[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s16/I3</td>
</tr>
<tr>
<td>4.575</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C38[0][A]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s16/F</td>
</tr>
<tr>
<td>4.746</td>
<td>0.170</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C38[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s13/I1</td>
</tr>
<tr>
<td>5.301</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R22C38[0][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s13/F</td>
</tr>
<tr>
<td>5.957</td>
<td>0.656</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C40[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s10/I1</td>
</tr>
<tr>
<td>6.474</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>R22C40[1][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_3_s10/F</td>
</tr>
<tr>
<td>6.887</td>
<td>0.414</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R22C39[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_2_s7/I3</td>
</tr>
<tr>
<td>7.349</td>
<td>0.462</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R22C39[1][B]</td>
<td style=" background: #97FFFF;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_2_s7/F</td>
</tr>
<tr>
<td>8.073</td>
<td>0.724</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C39[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_2_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R22C39[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_2_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R22C39[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_bitlevel/state_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.276, 39.233%; route: 3.293, 56.768%; tC2Q: 0.232, 3.999%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.074</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.834</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C23[2][A]</td>
<td>u_usb_audio/o_pcm_7_s0/CLK</td>
</tr>
<tr>
<td>1.712</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R27C23[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_7_s0/Q</td>
</tr>
<tr>
<td>1.834</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[7]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.077</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.837</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_28_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[2][B]</td>
<td>u_usb_audio/o_pcm_28_s0/CLK</td>
</tr>
<tr>
<td>1.712</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R27C25[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_28_s0/Q</td>
</tr>
<tr>
<td>1.837</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[28]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.077</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.837</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_23_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C24[0][A]</td>
<td>u_usb_audio/o_pcm_23_s0/CLK</td>
</tr>
<tr>
<td>1.712</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R27C24[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_23_s0/Q</td>
</tr>
<tr>
<td>1.837</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[23]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.077</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.837</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_16_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C24[2][A]</td>
<td>u_usb_audio/o_pcm_16_s0/CLK</td>
</tr>
<tr>
<td>1.712</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R27C24[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_16_s0/Q</td>
</tr>
<tr>
<td>1.837</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[16]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.077</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.837</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_8_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C23[1][B]</td>
<td>u_usb_audio/o_pcm_8_s0/CLK</td>
</tr>
<tr>
<td>1.712</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R27C23[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_8_s0/Q</td>
</tr>
<tr>
<td>1.837</td>
<td>0.125</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[8]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.198</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.958</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/audio_lo_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_audio_fifo/ram_block_ram_block_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C23[1][A]</td>
<td>u_usb_audio/audio_lo_1_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R14C23[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/audio_lo_1_s0/Q</td>
</tr>
<tr>
<td>1.958</td>
<td>0.245</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[6]</td>
<td style=" font-weight:bold;">u_audio_fifo/ram_block_ram_block_0_0_s/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[6]</td>
<td>u_audio_fifo/ram_block_ram_block_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[6]</td>
<td>u_audio_fifo/ram_block_ram_block_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.202</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.962</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[0][A]</td>
<td>u_usb_audio/o_pcm_5_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R26C23[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_5_s0/Q</td>
</tr>
<tr>
<td>1.962</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[5]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.203</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.964</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_17_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C24[1][B]</td>
<td>u_usb_audio/o_pcm_17_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C24[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_17_s0/Q</td>
</tr>
<tr>
<td>1.964</td>
<td>0.250</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[17]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.250, 55.351%; tC2Q: 0.202, 44.649%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.974</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[2][A]</td>
<td>u_usb_audio/o_pcm_2_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R29C25[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_2_s0/Q</td>
</tr>
<tr>
<td>1.974</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_31_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[2][B]</td>
<td>u_usb_audio/o_pcm_31_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C26[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_31_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[31]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_30_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[1][B]</td>
<td>u_usb_audio/o_pcm_30_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C26[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_30_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[30]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_29_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C26[0][B]</td>
<td>u_usb_audio/o_pcm_29_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C26[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_29_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[29]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_22_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[1][B]</td>
<td>u_usb_audio/o_pcm_22_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R29C26[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_22_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[22]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_21_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C24[2][B]</td>
<td>u_usb_audio/o_pcm_21_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C24[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_21_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[21]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_19_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[1][A]</td>
<td>u_usb_audio/o_pcm_19_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C25[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_19_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[19]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_18_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][A]</td>
<td>u_usb_audio/o_pcm_18_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R29C25[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_18_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[18]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C24[0][B]</td>
<td>u_usb_audio/o_pcm_15_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C24[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_15_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[15]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C26[0][B]</td>
<td>u_usb_audio/o_pcm_14_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R29C26[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_14_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[14]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R26C23[0][B]</td>
<td>u_usb_audio/o_pcm_13_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R26C23[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_13_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[13]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_12_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C24[1][A]</td>
<td>u_usb_audio/o_pcm_12_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C24[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_12_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[12]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[0][A]</td>
<td>u_usb_audio/o_pcm_11_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C25[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_11_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[2][B]</td>
<td>u_usb_audio/o_pcm_10_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R29C25[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_10_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[10]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.975</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C23[2][B]</td>
<td>u_usb_audio/o_pcm_9_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C23[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_9_s0/Q</td>
</tr>
<tr>
<td>1.975</td>
<td>0.262</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[9]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.216</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>1.977</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C25[2][A]</td>
<td>u_usb_audio/o_pcm_20_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R27C25[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_20_s0/Q</td>
</tr>
<tr>
<td>1.977</td>
<td>0.263</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[20]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.263, 56.595%; tC2Q: 0.202, 43.405%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.324</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.084</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.760</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/o_pcm_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][B]</td>
<td>u_usb_audio/o_pcm_6_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R29C25[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/o_pcm_6_s0/Q</td>
</tr>
<tr>
<td>2.084</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td style=" font-weight:bold;">u_usb_audio/bufo_bufo_0_0_s/DI[6]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.760</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R28[7]</td>
<td>u_usb_audio/bufo_bufo_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.371, 64.759%; tC2Q: 0.202, 35.241%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C39[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C39[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C39[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C33[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C33[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C33[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C39[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C39[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C39[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C39[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C36[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C36[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C36[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C36[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C36[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C36[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C36[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C36[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C36[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C30[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C30[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C30[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C30[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R27C30[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R27C30[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C30[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C30[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R30C30[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R30C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C30[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C30[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R31C30[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R31C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C32[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C32[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C32[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R29C27[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R29C27[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C27[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C27[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>15.073</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.831</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>18.903</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>2.271</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>2.503</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>3.831</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R25C27[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>16.667</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.938</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLK</td>
</tr>
<tr>
<td>18.903</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R25C27[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>16.667</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R30C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C39[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C39[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C39[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C33[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C33[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C33[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C39[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C39[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C39[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C36[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C36[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R30C36[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C36[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C36[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R30C36[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C36[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C36[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C36[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep00_resp_idx_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[2][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C30[2][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[1][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C30[1][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R27C30[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R27C30[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R30C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R30C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R30C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R30C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C30[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C30[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R31C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R31C30[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_cnt_9_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C32[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C32[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C32[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/tp_sta_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C29[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C29[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/sof_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[2][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R29C27[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R29C27[2][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_valid_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C27[0][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][B]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C27[0][B]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.047</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.569</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.522</td>
</tr>
<tr>
<td class="label">From</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>usb_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>usb_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R23C28[0][A]</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_s0/CLK</td>
</tr>
<tr>
<td>1.713</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>366</td>
<td>R23C28[0][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/usb_rstn_s0/Q</td>
</tr>
<tr>
<td>2.569</td>
<td>0.856</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[1][A]</td>
<td style=" font-weight:bold;">u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>428</td>
<td>PLL_R[1]</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>1.511</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R25C27[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0/CLK</td>
</tr>
<tr>
<td>1.522</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R25C27[1][A]</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_transaction/ep01_data_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_audio_fifo/wr_counter_4_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_audio_fifo/wr_counter_4_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_audio_fifo/wr_counter_4_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_audio_fifo/wr_counter_2_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_audio_fifo/wr_counter_2_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_audio_fifo/wr_counter_2_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_audio_fifo/rd_counter_green_sync0_3_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_audio_fifo/rd_counter_green_sync0_3_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_audio_fifo/rd_counter_green_sync0_3_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_audio_fifo/rd_counter_green_sync1_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_audio_fifo/rd_counter_green_sync1_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_audio_fifo/rd_counter_green_sync1_1_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_usb_audio/o_pcm_31_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_usb_audio/o_pcm_31_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_usb_audio/o_pcm_31_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_usb_audio/o_pcm_en_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_usb_audio/o_pcm_en_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_usb_audio/o_pcm_en_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_27_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_27_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_27_s1/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_packet_rx/rx_shift_4_s3</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_packet_rx/rx_shift_4_s3/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_packet_rx/rx_shift_4_s3/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_packet_rx/rx_shift_5_s3</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_packet_rx/rx_shift_5_s3/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_usb_audio/usbfs_core_i/u_usbfs_packet_rx/rx_shift_5_s3/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>6.570</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>7.570</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>usb_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_28_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>8.334</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>10.608</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_28_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td></td>
<td></td>
<td>usb_clk</td>
</tr>
<tr>
<td>16.667</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>u_clock_tree/u_usb_pll/rpll_inst/CLKOUT</td>
</tr>
<tr>
<td>18.178</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>u_usb_audio/usbfs_core_i/usb_rstn_cnt_28_s1/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>428</td>
<td>clk60mhz</td>
<td>9.750</td>
<td>2.274</td>
</tr>
<tr>
<td>202</td>
<td>audio_clk</td>
<td>316.308</td>
<td>2.274</td>
</tr>
<tr>
<td>128</td>
<td>volume_level[0]</td>
<td>321.439</td>
<td>1.611</td>
</tr>
<tr>
<td>84</td>
<td>ep00_resp_idx_Z[1]</td>
<td>10.678</td>
<td>1.425</td>
</tr>
<tr>
<td>83</td>
<td>rx_sta_Z</td>
<td>12.869</td>
<td>1.310</td>
</tr>
<tr>
<td>79</td>
<td>ep00_resp_idx_Z[2]</td>
<td>10.712</td>
<td>2.243</td>
</tr>
<tr>
<td>77</td>
<td>ep00_resp_idx_Z[4]</td>
<td>10.371</td>
<td>1.325</td>
</tr>
<tr>
<td>75</td>
<td>ep00_resp_idx_Z[0]</td>
<td>10.801</td>
<td>1.292</td>
</tr>
<tr>
<td>72</td>
<td>ep00_resp_idx_Z[3]</td>
<td>10.456</td>
<td>1.179</td>
</tr>
<tr>
<td>71</td>
<td>volume_level[1]</td>
<td>321.774</td>
<td>1.586</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R26C31</td>
<td>86.11%</td>
</tr>
<tr>
<td>R27C23</td>
<td>86.11%</td>
</tr>
<tr>
<td>R22C31</td>
<td>84.72%</td>
</tr>
<tr>
<td>R27C32</td>
<td>84.72%</td>
</tr>
<tr>
<td>R32C23</td>
<td>84.72%</td>
</tr>
<tr>
<td>R33C39</td>
<td>83.33%</td>
</tr>
<tr>
<td>R27C24</td>
<td>81.94%</td>
</tr>
<tr>
<td>R20C23</td>
<td>81.94%</td>
</tr>
<tr>
<td>R33C36</td>
<td>81.94%</td>
</tr>
<tr>
<td>R32C28</td>
<td>81.94%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name fpga_clk_in -period 20 -waveform {0 10} [get_ports {clk50mhz}]</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name usb_clk -period 16.667 -waveform {0 8.334} [get_nets {clk60mhz}]</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name audio_clk -period 325.521 -waveform {0 162.761} [get_nets {audio_clk}]</td>
</tr>
<tr>
<td>TC_CLOCK_GROUP</td>
<td>Actived</td>
<td>set_clock_groups -asynchronous -group [get_clocks {usb_clk}] -group [get_clocks {audio_clk}]</td>
</tr>
</table>
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